Process simulation for advanced stress and junction engineering

Abstract : For CMOS devices downscaling, sharp requirements have been defined by the International Technology Roadmap for Semiconductors (ITRS) in terms of drive and off state current and power density, making the geometric scaling a challenging task. The new vector largely adopted to extend Moore's law is the mobility enhancement through the introduction of stress by several techniques (Stress Liner, eSiGe embedded stressor, stress memorization). On the other side, a challenging experimental trade-off is being made on jonction processing to meet the sharp requirements in terms of resistance, abruptness and depth. Standard techniques (implantation and rapid thermal annealing) are being pushed to their limits whereas alternative techniques such as preamorphization, solid phase epitaxy (SPE), laser annealing and plasma doping are being optimized. As will be shown in this session of PULLNANO tutorials, many challenges are being faced by characterisation methods and metrology to support all of this intense research competition. TCAD more generally, and process simulation, in particular, have a complementary role to play to identify trade-off and evaluate the scalability. The progresses recently made by standard finite element based simulators for the modeling of implantation, diffusion and stress engineering will be reviewed and illustrated by examples from different european projects and from the literature. Furthermore, as the complexity increases with device downscaling, atomistic simulations are of interest to provide, more understanding and to perform computer experiments in cases where the time or atomic scale are very challenging for characterization. Several examples from our recent research work with molecular dynamics in PULLNANO will be presented.
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École thématique. ESSDERC/ESSCIRC 2008 Tutorial Session T2 Nanoelectronics : Characterisation for the nanoelectronics era, Edinburgh, UK, 2008, 53 p
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Contributeur : Christophe Krzeminski <>
Soumis le : mercredi 8 février 2012 - 15:10:13
Dernière modification le : jeudi 11 janvier 2018 - 06:19:14
Document(s) archivé(s) le : mercredi 14 décembre 2016 - 05:37:57

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  • HAL Id : cel-00667574, version 2

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Christophe Krzeminski, Evelyne Lampin. Process simulation for advanced stress and junction engineering. École thématique. ESSDERC/ESSCIRC 2008 Tutorial Session T2 Nanoelectronics : Characterisation for the nanoelectronics era, Edinburgh, UK, 2008, 53 p. 〈cel-00667574v2〉

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