Energy Efficient Hardware Loop Based Optimization for CGRAs

Chilankamol Sunny (1) , Satyajit Das (1) , Kevin J M Martin (2, 3) , Philippe Coussy (2, 3)

1 ITT Palakkad - Indian Institut of Technology [Palakkad]
2 Lab-STICC_ARCAD - Equipe Hardware ARchitectures and CAD tools
3 UBS - Université de Bretagne Sud

Research interest and industry investment in edge computing solutions have increased dramatically in recent years. Consequent quest for balanced performance, energy efficiency and flexibility bestowed surging popularity on Coarse Grained Reconfigurable Array (CGRA) architectures. To further improve the performance and energy efficiency, several hardware and software-based loop optimizations are adopted for CGRAs. In this paper, we propose a centralized hardware-based loop optimization technique to achieve better area and energy results compared to the previously implemented distributed version. Without incurring any performance degradation, area overhead against the reference architecture is reduced down to 1.5% for a 4×2 CGRA configuration. A maximum of 47.3% and an arithmetic mean of 27.2% reduction in energy consumption is attained by the centralized version of hardware loop compared to the baseline model employing software loop. Furthermore, the paper explores the co-existence of CGRA-specific hardware and software optimizations and their impact on loop efficiencies. Enhanced results are obtained by coupling loop unrolling with centralized hardware loop support. The combination allows achieving up to 68.7% reduction in energy consumption and 5.46× speed-up against the baseline model with no optimizations applied.

Mots clés: Coarse grained reconfigurable array (CGRA); Loop optimization; Hardware loop; Loop unrolling

Domaines: Architectures Matérielles [cs.AR]

Chilankamol Sunny, Satyajit Das, Kevin J M Martin, Philippe Coussy. Energy Efficient Hardware Loop Based Optimization for CGRAs. Journal of Signal Processing Systems, inPress, ⟨10.1007/s11265-022-01760-9⟩. ⟨hal-03704229⟩