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Communication Dans Un Congrès Année : 2022

Processor Extensions for Hardware Instruction Replay against Fault Injection Attacks

Résumé

The paper explores hardware supports for replaying instructions to protect processors against some fault injection attacks. A replay instruction is added to the instruction set of a small 32-bit RISC processor to allow the automatic and parametrized replay of sequences of instructions. Various detection elements are added to the processor, implemented on FPGA, and compared in terms of performances, cost and fault coverage. The proposed extension leads to significant improvements compared to software protections for a small silicon overhead.
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Dates et versions

hal-03599317 , version 1 (07-03-2022)

Identifiants

  • HAL Id : hal-03599317 , version 1

Citer

Noura Ait Manssour, Vianney Lapotre, Gogniat Guy, Arnaud Tisserand. Processor Extensions for Hardware Instruction Replay against Fault Injection Attacks. DDECS: 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, Apr 2022, Prague, Czech Republic. ⟨hal-03599317⟩
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