Parallel CN-VN processing for NB-LDPC decoders

Hassan Harb (1) , Cédric Marchand (2) , Ali Chamas Al Ghouwayel (3) , Laura Conde-Canencia (4) , E. Boutillon (5, 4)

1 Lab-STICC_ARCAD - Equipe Hardware ARchitectures and CAD tools
2 Lab-STICC - Laboratoire des sciences et techniques de l'information, de la communication et de la connaissance
3 Efrei - Efrei
4 Lab-STICC_CODES - Equipe CODES
5 UBS - Université de Bretagne Sud

In this paper, a novel and innovative approach to implement the check node and variable node phases of the EMS algorithm is proposed. The novelty is not only from the hardware side, but also from the algorithmic point of view. An unusual manner of processing some steps of the check and variable nodes are shown. The performance and implementation results are promising to dig deeper in this work. Compared to its serial counterpart, the synthesis results of the proposed architecture show a factor gain greater than two in terms of area efficiency, with negligible performance loss.

Mots clés: Channel coding; ASIC; NB-LDPC; Min-Sum

Domaines: Electronique

Hassan Harb, Cédric Marchand, Ali Chamas Al Ghouwayel, Laura Conde-Canencia, E. Boutillon. Parallel CN-VN processing for NB-LDPC decoders. IEEE Workshop on Signal Processing Systems (SiPS'2021), Oct 2021, combria, Portugal. ⟨hal-03474561⟩