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An efficient FIFO buffer management to ensure task level and effect-chain level data properties

Abstract : Real-time embedded systems (automotive, avionics,drones autopilots, etc.) are composed of numerous functional components that are continuously interacting via a variety of communication models where they intensively share data. For the overall functional correctness these systems must verify not only real-time scheduling requirements but they also must guarantee that the data being used are qualitatively correct. The quality of the data reflects the preservation of data related properties: temporal properties (i.e freshness, end-to-end latency, etc.) and integrity related properties (i.e data consistency). The proposed protocols to ensure such properties highly depend on the considered communication model (shared registers or large buffers) and the data access policy (directly or via local copies). In order to overcome this limitation, we provide in this paper, the means for managing the FIFO buffers to guarantee these data properties in a way that communication dependencies do not impact the tasks system scheduling order. We do so while considering the communication model presented in [14]. We provide methods computing a sufficient size for the considered buffers. Last but not least, an algorithm implementing the "last reader tags mechanism" together with the data temporal matching is provided and explained.
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https://hal.archives-ouvertes.fr/hal-03097920
Contributor : Cristian Maxim <>
Submitted on : Tuesday, January 5, 2021 - 3:19:34 PM
Last modification on : Tuesday, February 9, 2021 - 8:32:35 AM
Long-term archiving on: : Wednesday, April 7, 2021 - 9:29:12 AM

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Evariste Ntaryamira, Cristian Maxim, Therence Niyonsaba, Liliana Cucu-Grosjean. An efficient FIFO buffer management to ensure task level and effect-chain level data properties. ICESS 2020 - IEEE International Conference on Embedded Software and Systems, Dec 2020, Shanghai / Virtual, China. ⟨10.1109/ICESS49830.2020.9301518⟩. ⟨hal-03097920⟩

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